summaryrefslogtreecommitdiff
path: root/day10.go
blob: e0deaa0716e11c017e1a45df87efecf4f26a76bd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
package main

import (
	"bufio"
	"fmt"
	"log"
	"os"
	"regexp"
	"strconv"
)

type cpu struct {
	register  int
	cycle     int
	signalLog []int
}

func (c *cpu) instruction(op string, arg []string) {
	addx := func(arg []string) {
		x, err := strconv.Atoi(arg[0])
		if err != nil {
			log.Fatal("Got invalid arg to addx", err)
		}
		c.signalLog = append(c.signalLog, (c.cycle+1)*c.register, (c.cycle+2)*c.register)
		c.register += x
		c.cycle += 2
	}
	noop := func(arg []string) {
		c.signalLog = append(c.signalLog, (c.cycle+1)*c.register)
		c.cycle += 1
	}

	switch op {
	case "addx":
		addx(arg)
	case "noop":
		noop(arg)
	default:
		log.Fatal("Got unexpected input")
	}
}

func NewCpu() *cpu {
	return &cpu{
		register:  1,
		cycle:     0,
		signalLog: []int(nil),
	}
}

func main() {
	f, err := os.Open("day10.txt")
	if err != nil {
		log.Fatal("could open input file", err)
	}

	// Part 1: Keep a logahead of signals
	cpu := NewCpu()
	s := bufio.NewScanner(f)
	for s.Scan() {
		r := regexp.MustCompile(`(?P<instruction>\w+) ?(?P<arg>[-0-9 ]+)?`)
		m := r.FindStringSubmatch(s.Text())
		switch words := len(m[1:]); words {
		case 0:
			log.Fatal("Got unexpected input")
		case 1:
			cpu.instruction(m[1], []string(nil))
		default:
			cpu.instruction(m[1], m[2:])
		}
	}

	runningSum := 0
	for _, c := range []int{20, 60, 100, 140, 180, 220} {
		signal := cpu.signalLog[c-1]
		fmt.Println(fmt.Sprintf("cycle %d:", c), signal)
		runningSum += signal
	}
	fmt.Println("Part 1:", runningSum)

	// Part 2: Scan the signal log
	spri, te := 0, 2
	for cycle, signal := range cpu.signalLog {
		spri, te = (signal/(cycle+1))-1, (signal/(cycle+1))+1
		c := cycle % 40
		if spri <= c && c <= te {
			cpu.signalLog[cycle] = 1
		} else {
			cpu.signalLog[cycle] = 0
		}
	}
	for i := 0; i < len(cpu.signalLog); i += 40 {
		for _, visi := range cpu.signalLog[i : i+40] {
			if visi == 1 {
				fmt.Print("#")
			} else {
				fmt.Print(".")
			}
		}
		fmt.Println()
	}
}